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Features
* * * * * * * * * *
Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) 128-byte Page Mode Only for Write Operations Low-voltage and Standard-voltage Operation - 2.7 (VCC = 2.7V to 5.5V) - 1.8 (VCC = 1.8V to 5.5V) 10 MHz (5V), 5MHz (2.7V) and 2 MHz (1.8V) Clock Rate Block Write Protection Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection High Reliability - Endurance: 100K Write Cycles - Data Retention: >40 Years 8-lead PDIP, 8-lead EIAJ SOIC, 16-lead JEDEC SOIC and 8-lead Leadless Array Package
SPI Serial EEPROMs
256K (32,768 x 8) 512K (65,536 x 8)
Description
The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits each. The device is optimized for use in many industrial and commercial applications where high-speed, low-power, and low-voltage operation are essential. The AT25HP256/512 is available in a space saving 8-lead PDIP (AT25HP256/512), 8-lead EIAJ SOIC (AT25HP256), 16-lead JEDEC SOIC (AT25HP512) and 8-lead Leadless
AT25HP256 AT25HP512
(continued)
Pin Configurations
Pin Name CS SCK SI SO GND VCC WP HOLD Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input
CS SO NC NC NC NC WP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC HOLD NC NC NC NC SCK SI
16-lead SOIC
8-lead PDIP
CS SO WP GND 1 2 3 4 8 7 6 5 VCC
HOLD
8-lead SOIC
CS SO WP GND 1 2 3 4 8 7 6 5 VCC
HOLD
8-lead Leadless Array
VCC HOLD SCK SI 8 7 6 5 1 2 3 4 CS SO WP GND
SCK SI
SCK SI
Bottom View
Rev. 1113G-SEEPR-08/02
1
Array (AT25HP256/512) packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions. The AT25HP256/512 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with top 1/4, top 1/2 or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
32,768/65,536 x 8
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Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol COUT CIN Note: Test Conditions Output Capacitance (SO) Input Capacitance (CS, SCK, SI, WP, HOLD) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VOUT = 0V VIN = 0V
DC Characteristics
Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol VCC1 VCC2 VCC3 ICC1 ICC2 ISB1 ISB2 ISB3 IIL IOL VIL
(1)
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
Test Condition
Min 1.8 2.7 4.5
Typ
Max 3.6 5.5 5.5
Units V V V mA mA A A A A A V V V V
VCC = 5.0V at 5 MHz, SO = Open Read VCC = 5.0V at 5 MHz, SO = Open Write VCC = 1.8V, CS = V CC VCC = 2.7V, CS = V CC VCC = 5.0V, CS = V CC VIN = 0V to VCC VIN = 0V to VCC, TAC = 0C to 70C -3.0 -3.0 -0.6 VCC x 0.7 4.5V VCC 5.5V 1.8V VCC 3.6V IOL = 3.0 mA IOH = -1.6 mA IOL = 0.15 mA IOH = -100 A VCC - 0.2 VCC - 0.8
6.0 4.0 0.1 0.2 2.0
10.0 7.0 2.0 2.0 5.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4
VIH(1) VOL1 VOH1 VOL2 VOH2 Note:
0.2
V V
1. VIL and V IH max are reference only and are not tested.
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AC Characteristics
Applicable over recommended operating range from TA = -40C to +85C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol fSCK Parameter SCK Clock Frequency Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 40 80 200 40 80 200 50 100 250 50 100 250 50 100 250 12 20 50 10 20 50 25 50 100 25 50 100 0 0 0 0 0 0 40 80 200 Min 0 0 0 Max 10 5 2 2 2 2 2 2 2 Units MHz
tRI
Input Rise Time
s
tFI
Input Fall Time
s
tWH
SCK High Time
ns
tWL
SCK Low Time
ns
tCS
CS High Time
ns
tCSS
CS Setup Time
ns
tCSH
CS Hold Time
ns
tSU
Data In Setup Time
ns
tH
Data In Hold Time
ns
tHD
Hold Setup Time
ns
tCD
Hold Hold Time
ns
tV
Output Valid
ns
tHO
Output Hold Time
ns
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AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40C to +85C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol tLZ Parameter Hold to Output Low Z Voltage 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 100K Min 0 0 0 Max 100 200 300 100 200 300 100 100 250 10 10 10 Units ns
tHZ
Hold to Output High Z
ns
tDIS
Output Disable Time
ns
tWC
Write Cycle Time
ms
Endurance(1) Note:
4.5 - 5.5 2.7 - 5.5 1.8 - 5.5 1. This parameter is characterized and is not 100% tested. 5.0V, 25C, Page Mode
Write Cycles
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Serial Interface Description
MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25HP256/512 always operates as a slave. TRANSMITTER/RECEIVER: The AT25HP256/512 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25HP256/512, and the serial output pin (SO) will remain in a high impedance state un til the falling edge of CS is de tected a gain. This will reinitialize the serial communication. CHIP SELECT: The AT25HP256/512 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. H O LD : Th e H OLD p in is u se d in co n jun ctio n w it h the C S pin to s e le ct th e AT25HP256/512. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is "1", all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is "0". This will allow the user to install the AT25HP256/512 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to "1".
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SPI Serial Interface
Functional Description
AT25HP256/512
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The AT25HP256/512 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25HP256/512 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 1. Instruction Set for the AT25HP256/512
Instruction Name WREN WRDI RDSR WRSR READ WRITE Instruction Format 0000 X110 0000 X100 0000 X101 0000 X001 0000 X011 0000 X010 Operation Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 2. Status Register Format
Bit 7 WPEN Bit 6 X Bit 5 X Bit 4 X Bit 3 BP1 Bit 2 BP0 Bit 1 WEN Bit 0 RDY
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Table 3. Read Status Register Bit Definition
Bit Bit 0 (RDY) Bit 1 (WEN) Bit 2 (BP0) Bit 3 (BP1) Definition Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. See Table 4. See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25HP256/512 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 4. Block Write Protect Bits
Status Register Bits Level 0 1(1/4) 2(1/2) 3(All) BP1 0 0 1 1 BP0 0 1 0 1 Array Addresses Protected AT25HP256/512 None 6000 - 7FFF/C000 - FFFF 4000 - 7FFF/8000 - FFFF 0000 - 7FFF/0000 - FFFF
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is "1". Hardware write protection is disabled when either the WP pin is high or the WPEN bit is "0." When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to "0", as long as the WP pin is held low. Table 5. WPEN Operation
WPEN 0 0 1 WP X X Low WEN 0 1 0 ProtectedBlocks Protected Protected Protected UnprotectedBlocks Protected Writable Protected Status Register Protected Writable Protected
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Table 5. WPEN Operation
WPEN 1 X X WP Low High High WEN 1 0 1 ProtectedBlocks Protected Protected Protected UnprotectedBlocks Writable Protected Writable Status Register Protected Protected Writable
READ SEQUENCE (READ): Reading the AT25HP256/512 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUENCE (WRITE): In order to program the AT25HP256/512, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address and the data (D7-D0) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW to High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle. The AT25HP256/512 is capable of a 128-byte PAGE WRITE operation. After each byte of data is received, the seven low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 128-bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25HP256/512 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6. Address Key
Address AN Don't Care Bits AT25HP256/512 A14 - A 0 / A15 - A0 A 15 / none
NOTE: 128-byte PAGE WRITE operation only. Content of the page in the array will not be guaranteed if less than 128 bytes of data is received (byte write is not supported).
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Timing Diagrams (for SPI Mode 0 (0,0))
Synchronous Data Timing
VIH CS VIL tCSS VIH SKC tWH VIL tSU SI VIH VALID IN VIL tV VOH SO VOL
HI - Z
tCS
tCSH tWL
tH
tHO
tDIS
HI - Z
WREN Timing
CS
SCK
SI
SO
WRDI Timing
CS
SCK
SI
WRDI OP-CODE
SO
HI-Z
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RDSR Timing
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK
SI
INSTRUCTION
SO
HIGH IMPEDANCE
DATA OUT
7 6 5 4 3 2 1 0
MSB
WRSR Timing
READ Timing
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WRITE Timing (AT25HP256)
CS 0 SCK BYTE ADDRESS SI INSTRUCTION 15 14 13 ... 3 2 1 0 7 6 1ST BYTE DATA IN 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SO
HIGH IMPEDANCE
PAGE WRITE Timing (AT25HP512)
CS 0 SCK BYTE ADDRESS 1st BYTE DATA IN SI INSTRUCTION 15 14 13 12 3 2 1 0 7 6 5 128th BYTE DATA IN 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 20 21 22 23 24 25 26 1043 1044 1045 1046 1047
SO
HIGH IMPEDANCE
HOLD Timing
CS tCD SCK tHD HOLD tHZ SO tLZ tHD tCD
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AT25HP256 Ordering Information
tWC (max) (ms) 10 ICC (max) (A) 4000 ISB (max) (A) 2.0 fMAX (kHz) 5000 Ordering Code AT25HP256-10CI-2.7 AT25HP256-10PI-2.7 AT25HP256W-10SI-2.7 AT25HP256-10CI-1.8 AT25HP256-10PI-1.8 AT25HP256W-10SI-1.8 Package 8CN3 8P3 8S2 8CN3 8P3 8S2 Operation Range Industrial (-40C to 85C) Industrial (-40C to 85C)
10
3000
2.0
2000
Package Type 8CN3 8P3 8S2 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8-lead, 0.200" Wide, Plastic Small Outline Package (EIAJ) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V)
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AT25HP512 Ordering Information
Ordering Code AT25HP512-10CI-2.7 AT25HP512CI-10CI-2.7 AT25HP512-10PI-2.7 AT25HP512W2-10SI-2.7 AT25HP512-10CI-1.8 AT25HP512CI-10CI-1.8 AT25HP512-10PI-1.8 AT25HP512W2-10SI-1.8 Note: Package 8CN3 8CN1 8P3 16S2 8CN3 8CN1 8P3 16S2 Operation Range Industrial (-40C to 85C)
Industrial (-40C to 85C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
Package Type 8CN3 8CN1 8P3 16S2 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8-lead, 0.300" Wide, Leadless Array Package (LAP) 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V)
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Packaging Information
8CN3 - LAP
Marked Pin1 Indentifier
E
D
A A1
Top View
0.10 mm TYP
Side View
L1
Pin1 Corner
8
1
e
7 2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.36 5.89 4.83 NOM 1.04 0.34 0.41 5.99 4.93 1.27 BSC 0.56 REF 0.62 0.92 0.67 0.97 0.72 1.02 1 1 MAX 1.14 0.38 0.46 6.09 5.03 1 NOTE
6
3
A
b
5 4
A1 b D E
e1
L
e e1 L L1
Bottom View
Note: 1. Metal Pad Dimensions.
11/14/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN3, 8-lead, (6 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN3 REV. A
R
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8CN1 - LAP
Marked Pin1 Indentifier
E
D
A A1
Top View
0.10 mm TYP
Side View
L1
Pin1 Corner
8
1
e
7 2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.36 7.90 4.90 NOM 1.04 0.34 0.41 8.00 5.00 1.27 BSC 0.60 REF 0.62 0.92 0.67 0.97 0.72 1.02 1 1 MAX 1.14 0.38 0.46 8.10 5.10 1 NOTE
6
3
A
b
5 4
A1 b D E
e1
L
e e1 L L1
Bottom View
Note: 1. Metal Pad Dimensions.
11/13/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN1 REV. A
R
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8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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8S2 - EIAJ SOIC
1
H
N
Top View
e
b
A
D
Side View
SYMBOL
COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE
A
1.78 0.05 0.35 0.18 5.13 5.13 7.62 0.51 1.27 BSC
2.03 0.33 0.51 0.25 5.38 5.41 8.38 0.89 4 2, 3 5 5
A1 L E
C
A1 b C D E
End View
H L e
Notes: 1. 2. 3. 4. 5.
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.
5/2/02 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. REV. B
R
2325 Orchard Parkway San Jose, CA 95131
8S2
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16S2 - JEDEC SOIC
C
1
E
H
N
Top View
A1
End View
e b A D
SYMBOL COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A1 b C D E H L e
L
0.0926 0.0040 0.0130 0.0091 0.3977 0.2914 0.3940 0.0160 0.050 BSC
0.1043 0.0118 0.0200 0.0125 0.4133 0.2992 0.4190 0.050 4 2 3 5
Side View
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AA for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "B", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 1/9/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 16S2, 16-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
DRAWING NO. 16S2
REV. A
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Atmel Headquarters
Corporate Headquarters
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600
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Microcontrollers
2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is a registered trademark of Atmel. Terms and product names in this document may be trademarks of others. Printed on recycled paper.
1113G-SEEPR-08/02 xM

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